Chapter 1. Features and Capabilities

This chapter describes the features and capabilities of the DMediaPro Board.
The following topics are covered:

DMediaPro Board Panel

Figure 1-1 shows the DMediaPro Board with its connectors and LEDs. The board ships with two Low Voltage Differential Signaling ( LVDS) cables that interface with the SGI Video Breakout Box (VBOB).

Figure 1-1. DMediaPro Board Panel

DMediaPro Board Panel

Input/Output (I/O)

The DMediaPro system uses the VBOB for analog genlock connections and Serial Digital Interface ( SDI) High Definition (HD) and Standard Definition (SD) video I/O.


Note: For information on I/O and genlock timing features, see Chapters 3 and 5 in this guide. For a complete description of the VBOB, including all the I/O connectors, see the SGI Video Breakout Box Owner's Guide.


Supported Video Formats

The DMediaPro Board supports video formats defined by the Advanced Television Standards Committee (ATSC), as well as several formats defined for High Definition digital motion pictures and post production. In addition, the board supports several Standard Definition formats. These formats can have pixel clocks of up to 74.25 MHz. These formats include support for:

  • 1080p, 1080i, 720p, 576i, and 480i video formats

  • 23.98, 24, 25, 29.97, 30, 59.94, and 60 Hz vertical rates

  • 16 x 9 and 4 x 3 aspect ratios

Examples of supported formats are SMPTE 274M (interlaced and progressive),
SMPTE 296 (progressive), ITU-R BT.601-5 (interlaced), SMPTE 260M, and SMPTE 240M.


Note: ITU-R BT.601-5 is also known as Rec. 601 and CCIR 601.

Table 1-1 lists the DMediaPro Board video timings that are supported for the first release of the board.


Note: In the third column of the table, the prefix, ML_TIMING_ should appear before each timing, but was omitted to avoid redundancy.


Table 1-1. Supported Video Timings

Description

Frame Rate

Timing

1920x1080 interlaced

30/1.001 Hz

1125_1920x1080_5994i

1280x720 progressive

60/1.001 Hz

750_1280x720_5994p

1280x720 progressive

60 Hz

750_1280x720_60p

1920x1080 interlaced

25 Hz

1125_1920x1080_50i

1920x1080 interlaced

30 Hz

1125_1920x1080_60i

1920x1080 progressive

24 Hz

1125_1920x1080_24p

1920x1080 progressive

24/1.001 Hz

1125_1920x1080_2398p

1920x1080 progressive

25 Hz

1125_1920x1080_25p

1920x1080 progressive segmented frame

25 Hz

1125_1920x1080_25PsF

1920x1080 progressive segmented frame

24 Hz

1125_1920x1080_24PsF

1920x1080 progressive segmented frame

24/1.001 Hz

1125_1920x1080_2398PsF

1920x1035 interlaced

30/1.001 Hz

1125_1920x1035_5994i

720 x 487 ( NTSC)

30/1.001 Hz

525

720 x 576 ( PAL)

25 Hz

625

In Progressive segmented Frame (PsF) formats, the progressive frame is transmitted as two fields that are from the same progressive scan, while in interlaced formats the two fields are temporally displaced.

All formats are 8-bit or 10-bit. These formats are used for content creation and telecine output, and support serial-parallel conversion.

Other Features

The DMediaPro Board includes the following features:

  • Programmable field size (see “Re-sizing Field Height” in Chapter 5).

  • YCrCb with 8- or 10-bits per component (4:2:2 or 4:4:4 sampling rates).

  • Alpha channel support.

  • Video interface support for RGB 8- or 10- bits.

  • Support for up to 64 bits/pixel RGB in memory.

  • Real-time “transparent” color space conversion in ITU-R Rec. 601, ITU-R Rec. 709, SMPTE 240M, and key scaling.

  • User-programmable horizontal and vertical phase adjustment of the output video.

  • Unadjusted System Time ( UST) and Media Stream Count (MSC) support on input and output.

  • Gamma correction support through user-downloadable 13-bit-wide lookup table.

  • 3/2 pulldown mode on output.

  • Full Frame mode supported at SD rates (270 MB/sec) for compressed image I/O (for HDcam, DVcam, and other compressed HD formats).

  • Packing modes (see Table 1-2). For VL/ML packing conversions, see “ML_IMAGE_PACKING” in Chapter 5.

    Table 1-2. Supported Packing Modes

    ML_IMAGE_PACKING

    ML_IMAGE_SAMPLING

    ML_PACKING_8

    ML_SAMPLING_422

    ML_PACKING_8_3214

    ML_SAMPLING_422

    ML_PACKING_10

    ML_SAMPLING_422

    ML_PACKING_10_3214

    ML_SAMPLING_422

    ML_PACKING_10in16L

    ML_SAMPLING_422

    ML_PACKING_10in16L_3214

    ML_SAMPLING_422

    ML_PACKING_10in16R

    ML_SAMPLING_422

    ML_PACKING_10in16R_3214

    ML_SAMPLING_422

    ML_PACKING_10_10_10_2

    ML_SAMPLING_4224

    ML_PACKING_10_10_10_2_3214

    ML_SAMPLING_4224

    ML_PACKING_8

    ML_SAMPLING_444

    ML_PACKING_8_R

    ML_SAMPLING_444

    ML_PACKING_S12in16L

    ML_SAMPLING_444

    ML_PACKING_S12in16R

    ML_SAMPLING_444

    ML_PACKING_8

    ML_SAMPLING_4444

    ML_PACKING_8_R

    ML_SAMPLING_4444

    ML_PACKING_10_10_10_2

    ML_SAMPLING_4444

    ML_PACKING_10_10_10_2_R

    ML_SAMPLING_4444


Theory of Operation

The DMediaPro Board (DM2 and DM3) interfaces High Definition (HD), Standard Definition (SD), and Serial Digital Transport Interface (SDTI) video formats to the SGI XIO bus. The board is the second generation of the HD I/O architecture.

The DMediaPro Board provides a full-duplex, dual-link, High Definition (HD) and Standard Definition (SD) video interface between the SGI 400 MHz Crosstalk XIO bus and the DMediaPro LVDS links. The LVDS links run at seven times the programmed video rates, from 189 MHz to 519.75 MHz, corresponding to seven times the 27 MHz to 74.25 MHz video link rates. The board uses an internal 100 MHz bus architecture, which is common to both the SGI HD I/O Board and the SGI Infinite Reality graphics systems. This architecture is based on the SGI "XG" ASIC. The board's video input and output pipes interface to this internal bus through DMA engines contained in the SGI "GIF" FPGA. GIF also controls all other FPGAs through the local bus controller and the PIO unit. The various packings and color spaces are supported by the packers, unpackers, and the input and output color space converter FPGAs.

The board also supports Downloadable Lookup Tables (LUTs) for linear, log, and gamma correction. Video input and output format and control are contained in the VIF and HDOC FPGAs, respectively. The CLINK FPGA contains the LVDS channel link control and the status logic.

Figure 1-2 is a simplified top-level diagram of the DMediaPro Board.

Figure 1-2. DMediaPro Board Top-level Diagram

DMediaPro Board Top-level Diagram